1. Field of the Invention
The present invention relates to a memory test circuit and a semiconductor integrated circuit into which the memory test circuit is incorporated, and more particularly to a memory test circuit suitable for being built in a hybrid integrated circuit of a microprocessing unit (MPU) and a memory and the hybrid IC of MPU and the memory including the memory test circuit.
2. Description of the Related Art
As semiconductor technology makes progress, the performance of a semiconductor integrated circuit is enhanced year by year and the operational frequency of a microprocessing unit (MPU) currently reaches several hundreds MHz. However, the operational frequency of a bus between MPU and a memory LSI is as low as scores MHz because of restriction such as the delay time of wiring on a printed board. Therefore, when an MPU chip and a memory LSI chip are connected via wiring on a printed board, the performance of MPU cannot be sufficiently utilized. To enhance data transfer rate via wiring on a printed board, a trial of widening bus width (increasing the number of buses) is also made, however, there is a limit because of difficulty in designing a printed board and the restriction of the number of pins in a package. Therefore, recently, hybrid LSI of MPU and a memory in which MPU and the memory are integrated on the same semiconductor substrate attracts attention according to pages 46-53 in the March number of Nikkei Micro Device published in 1996.
As MPU and a memory are not connected via wiring on a printed board but directly connected via the internal bus of a semiconductor chip in such hybrid LSI of MPU and the memory, the length of the bus is reduced and therefore, the operational frequency of the bus can be speed up. Bus width can be also readily widened. Therefore, the velocity performance of a system can be enhanced. Approximately scores-Mbit dynamic RAM (DRAM) is mounted on hybrid LSI of MPU and a memory which is recently disclosed. It is conceivable that as semiconductor miniaturizing technology makes progress, the capacity of a mounted memory will be greatly increased the in future.
When the capacity of a mounted memory is increased, time required for testing the memory is extended. In addition, in hybrid LSI of MPU and a memory, as generally, an internal memory cannot be directly accessed from an external device and is accessed via MPU under the control of MPU, a memory test circuit for directly outputting data on an internal bus connecting the memory and MPU to an external device without via MPU and for directly supplying data from an external device to the internal bus without via MPU is required to test the memory separately from MPU.
Therefore, it is conceivable that a device to make a memory test in such LSI in short time will be more important in the future.